Aspects of this application relate in general to electronic circuitry and in particular to methods and circuitry for optimizing the performance of SRAM memory devices. Recently SRAM memory devices are increasingly used for “on-board” data storage for highly integrated circuits, which may form a single chip solution for a particular system. These integrated circuits typically have several functional blocks which together form a complete system, and are sometimes called a “System on a Chip” or “SOC.” Use of SOCs reduces the number of components, the board area, and the interconnections between packaged integrated circuits on a circuit board, thereby increasing performance and reliability and reducing the size of the components. SRAM memory is particularly useful for an SOC as it has the advantages of relatively fast data access and static data storage in a memory, and SRAM maintains the stored data so long as power is present. Dynamic RAM (DRAM) is sometimes used as data storage as it is far denser than SRAM but DRAM has to be refreshed periodically or data errors occur due to inherent leakage currents, and DRAM can have longer data access time. DRAM is also typically manufactured in specialized semiconductor processes, making integration of DRAM on board SOC devices more difficult. In contrast, SRAM cells are easily manufactured within an integrated circuit alongside the other logic circuitry used to form microprocessor or microcontroller blocks, data registers, dedicated functional blocks such as ALUs, shifters, and the like, that are used as functional blocks on an SOC.
FIG. 1 is a block diagram of circuitry for use with SRAM devices. FIG. 1 depicts, as an illustrative example of the use of on-board SRAM memory, an SOC for an application such as an “internet of things” or “IoT” application. The SOC has several functional blocks which, in prior generation devices, might have been provided as separate integrated circuits but which in recent years are increasingly formed together on an SOC. Recently, memory devices and particularly SRAM memories are increasingly included “on board” the SOC.
In FIG. 1, the non-limiting example SOC includes sensors 101, radio transceivers 103, analog front end or “AFE” 105, power management or “PM” 107, a microcontroller or “μC” 109, non-volatile memory or “NVM” 111, and static RAM 113. SRAM (“RAM” 113) can be used in any number of applications, and this example SOC 100 is presented for illustration purposes only. Also, SOC 100 can include more, fewer, or different functional blocks. The sensors 101 can be any one of a variety of sensor types such as sensors sensing pressure, temperature, sound, light, user input from a control panel, etc. Radios 103 can implement a variety of interfaces between the SOC 100 and external devices using a variety of over the air interfaces. Examples of over the air interfaces include, for non-limiting examples, Bluetooth, WiFi, WiMAX, cellular communications such as 3G, 4G, LTE, radio frequency standards such as used for RFID tags, and the like. Analog front end “AFE” 105 can implement a variety of analog to digital conversion functions such as sigma delta analog to digital converters (ADCs), recursive and pipelined ADCs, and the like used for receiving analog signals from the sensors, for example, and for outputting digital data for use by other blocks in the SOC. Power management “PM” 107 can implement a variety of power management functions, such as clock speed control, battery management, sleep, wait states, etc. to extend the life of a battery for a portable device application, for example. Microcontroller 109 can be implemented using a wide variety of existing processors provided as cores or macros such as mixed signal processors (MSPs), digital signal processors (DSPs), reduced instruction set machines such as RISC cores, advanced RISC machines such as ARM cores, general purpose microprocessors, and microcontrollers. Simple state machines can also be used as microcontroller 109. Various aspects of the present invention are compatible with a wide variety of applications. In some applications, portable devices including SOCs typically have sleep, stand by, and other power saving modes typically used in order to preserve battery life. These power saving modes often involve reducing a clock frequency, since lower clock frequencies save power in most integrated circuit devices.
The memory portions of the example SOC 100 include a non-volatile memory portion NVM 111. NVM 111 can be implemented using EEPROM, E2PROM, FLASH, ROM and even fixed data storage such as hardwired ROM or programmable fuse or anti-fuse data storage. The NVM 111 can be used to store fixed data words such as program instructions for the microcontroller 109, code words, security keys, and the like. Programmable non-volatile memory such as EEPROM or FLASH can be used in a prototyping environment to develop program instructions for a particular application of SOC 100. Later versions of the SOC 100 can be produced with fixed data in non-volatile memory, such as a ROM.
RAM 113 can be implemented with an SRAM memory. SRAM memory is increasingly used to store data on board an SOC. The SRAM memory can store register values, computational results, program words and data which need to be retrieved by other blocks in the system. SRAM 113 is typically arranged on a memory bus with an address input, and read/write control line that are latched into the SRAM by a clock input signal. The read operations for the SRAM 113 result in data words that are output from the SRAM 113 which are valid at the end of a memory cycle. Typically the data valid time will occur sometime before the next rising edge of the clock input signal, so that the system can clock the valid SRAM data as input to other functional blocks. The minimum access time needed for the SRAM to receive the address and read request inputs, decode the address to select an addressed SRAM cell with rows and columns, sense the differential voltage and amplify the data, and output the data, referred to as the memory cycle, can be the limiting factor on the maximum system clock speed for the SOC. Improvements in the SRAM memory cycle time are therefore needed to enable the increase of the operational speed of devices using SRAMs.
FIG. 2 is a block diagram of a prior known solution SRAM device 200. FIG. 2 is presented for use in describing the operations of the prior known solutions. SRAM 200 receives as input signals an address field labeled “Address,” a data input field labeled “Write Data” used for write operations to the SRAM 200, a read write control input labeled “Read/Write” indicating that a particular access operation is a read or write operation, and a clock signal labeled “CLK.” There are various additional control signals input to the SRAM 200 for tailoring the operation of the SRAM 200 for different operating conditions, including input control signals labeled “OFF, ON, Sleep,” and other inputs used to reduce or increase the power used in different operating conditions. Power reduction is increasingly important for battery operated portable devices such as tablet computers, smart phones, web browsing devices, digital cameras, camcorders and the like.
FIG. 3 illustrates a timing diagram for an SRAM device such as SRAM 200. FIG. 3 illustrates the memory cycle time in a timing diagram when operating in a READ operation. Following a rising clock edge on the input clock signal CLK, a memory access is performed. During the first portion of the memory access, the data at the outputs of the SRAM 200 is not valid. This is shown by the shading on the output signal Q in FIG. 3. The internal operations of the memory device that occur prior to valid data being available at the output of the SRAM device include: decoding a first portion of the address field to determine which row of memory cells is being addressed in row decoders, firing the selected word line signal to cause the row of memory cells to share data with columns of complementary bit lines coupled to the SRAM cells, selecting one or more columns (depending on the width of the memory word, which may be a X1, X4, X8, or X16 word width) using a second portion of the address field in column decoders, and enabling the selected columns to be sensed by a plurality of sense amplifiers using a column select or Y-select multiplexer. The sense amplifiers then latch the differential voltage signal that is on the complementary bit lines and the sense amplifiers amplify the signal to a logic level voltage that is then valid data presented at the data output signals Q of the SRAM 200. The timing diagram in FIG. 3 shows the data arriving at the output as “Q0 Data Valid.” In the timing diagram, two sequential data accesses are illustrated. The time that is needed from the rising edge of the CLK signal to the valid data Q0 Data Valid, and Q1 Data Valid, at the outputs is the memory access time, and is sometimes referred to as the performance metric “Clk-to-Q” time.
Each conventional SRAM memory access involves several operations that happen internally within the SRAM device 200 in a particular sequence. To further describe the SRAM operations, FIG. 4 depicts in a simple circuit diagram a single memory cell 400 and a precharge circuit 401.
FIG. 4 is a circuit diagram of an SRAM cell. In FIG. 4 a six transistor SRAM cell 400 is depicted. Two cross coupled CMOS inverter devices are formed by the P-type transistor P1 and N-type transistor M1, forming a first inverter, and P-type transistor P2 and N-type transistor M2 forming a second inverter. The cross coupled inverters form a storage latch that stores a datum on nodes SNT and SNC as complementary voltages. Depending on the architecture of the system, the stored voltages can correspond either to a logic one or to a logic zero. Two access transistors labeled IN1 and IN2 selectively couple the storage nodes SNT and SNC to two complementary bit lines BLT and BLC when there is a high voltage on the word line WL. Because the four transistors P1, M1, P2, M2 making up the two inverters and the access transistors IN1 and IN2 form a complete SRAM cell, this SRAM cell is known as a “6T” SRAM cell. Aspects of the present application can also be applied to SRAM architectures using other arrangements, such as an 8T SRAM cell. 8T SRAM cells include the transistors of FIG. 4 and additionally 8T SRAM cells have separate read and write access ports. In aspects of the present application, an SRAM device can be formed using 8T SRAM cells as well as with the 6T SRAM cells shown here.
FIG. 4 further depicts a word line WL shown running horizontally across the SRAM cell 400. (Note that the orientation of the word lines or row lines as ‘horizontal’ refers only to the example circuit diagram, and the bit lines are often described as arranged in a “vertical” direction, however in an actual physical implementation of the SRAM cells and of SRAM arrays, these signals can be oriented in various ways and the word line and bit lines can be oriented in any number of directions.) A plurality of the SRAM cells will be arranged along a plurality of word lines WL in a typical SRAM array. Current SRAM arrays can include thousands, tens of thousands and even more SRAM cells. The example SRAM cell 400 is further coupled to a pair of complementary bit lines labeled BLT, and BLC, arranged in another direction. In an example SRAM circuit the columns of bit lines can be oriented in a “vertical” direction. In a typical SRAM array, a plurality of SRAM cells can be arranged along columns, each column having a pair of complementary bit lines. An address directed to the SRAM array specifies a row of cells and a column (or a group of columns) of cells to be written to, or read from, for each access to the SRAM device. The SRAM device architecture can be an X1, X4, X8 or X16 architecture, as examples, depending on the number of columns of SRAM cells that are accessed in each cycle.
In operation, a read cycle to access the data (referred to as a “datum”) stored in the SRAM cell 400 begins by raising the voltage on the word line or “firing” the word line labeled WL. When the word line WL has a high voltage on it greater than a threshold voltage, the access transistors IN1, and IN2, which can be referred to as pass transistors, turn on and couple the bit lines BLT and BLC to the storage nodes SNT and SNC in the SRAM cell 400. Once the access transistors IN1 and IN2 are active, the voltages on the bit lines BLT and BLC will move apart as the differential voltage stored in the SRAM cell 400 is shared with the bit lines. One of the bit lines BLT, BLC will increase by a differential voltage, and the other will decrease, depending on the value of the datum stored as a voltage on the complementary storage nodes SNT and SNC. When the voltage levels on the bit lines spread apart due to being coupled to the storage nodes by a charge sharing operation, the slight difference voltage can be sensed by a column sense amplifier (not shown) coupled to the bit lines BLT and BLC, which will amplify the difference voltage to a full logic level.
The SRAM cell 400 outputs only a small differential voltage onto the bit lines BLT and BLC. Sense amplifiers (not shown) are coupled to the bit lines during a memory access and sense the small differential voltage. Because the differential voltages stored in the SRAM cells are very small signal level voltages, the bit lines are first precharged to a common precharge voltage. In FIG. 4, precharge transistors IP1 and IP2 are shown in precharge circuit 401 and are coupled to the bit lines B/LT and B/LC. Each column of SRAM cells can share a precharge circuit over all of, or a portion of, the SRAM array. When a control signal PRE_BL is active, these precharge transistors couple a voltage supply labeled Vprecharge to both of the bit lines BLC and BLT. Each one of the bit line pairs in an SRAM array requires a precharge circuit such as circuit 401, however many SRAM cells can be coupled to the columns formed by the bit line pairs and share the same precharge circuit.
In operation, the precharge control signal PRE_BL in a conventional SRAM array is active at least once in each memory access cycle, typically, at the end of the current memory access cycle and typically before the next memory cycle begins. The precharge voltage Vprecharge can be a voltage between a minimum and maximum supply voltage level, such as Vdd, or Vdd/2. When the control signal PRE_BL is active, the bit lines BLT and BLC are both precharged to this voltage Vprecharge.
FIG. 5 is a block diagram of an SRAM device presented in order to further explain the operation of the SRAM memory devices. In FIG. 5, an array of SRAM cells 501a-501c are shown disposed in a first column, 503a-503c are disposed in a second column, and are arranged in rows a-c with word lines labeled WLa-WLc in an SRAM device 500. Note that in an actual production SRAM device there can be thousands or tens of thousands of SRAM cells, or more. The word lines WLa-WLc are output by the row decoder ROW DEC. numbered 505. A column decoder labeled COL. DEC. numbered 507 outputs control lines to a multiplexer Y-SEL numbered 509 that receives as inputs bit line pairs BLT0, BLC0 to BLTn, BLCn, and that outputs a pair of complementary Y select complementary outputs labeled YT, YC to a sense amplifier labeled Sense and numbered 513. The sense amplifier 513 latches the differential voltage on the selected bit line pair and outputs the signal DATA.
Each of the true and complement bit line pairs BLT0, BLC0 to BLTn, BLCn, are coupled to a corresponding precharge circuit numbered 5110-511n. A precharge control circuit labeled PRE; and numbered 515, outputs the precharge control signal PRE_BL to the precharge circuits.
In operation, the SRAM 500 memory access cycle begins when a clock signal CLK goes high. The address input signal ADD is latched and row decoder ROW DEC. 505 begins decoding a portion of the address field and outputs a high voltage on a selected one of the word lines WLa-WLc, selected by a portion of the address. The column decoder COL. DEC. 507 begins by decoding a second portion of the address field ADD and outputs a select signal to the Y-sel. multiplexer 509. The Y-sel. multiplexer determines which ones of the bit line pairs BLT0, BLC0-BLTn, BLCn is selected.
When the word line voltage on the selected word line WLa-WLc rises, the complementary bit lines for the SRAM cells along the selected row are coupled to the storage nodes within each of the SRAM cells. The voltages on the complementary bit line pairs in each column begin to spread apart as the differential voltage in the SRAM cells is shared with the bit lines. Each bit line along the active row will take the differential voltage value of the storage nodes of the SRAM cells in the corresponding columns.
The column select multiplexer 509 labeled Y-SEL then couples the selected bit line pair to the complementary output signals YT and YC. COL. DEC. 507 determines which column is selected based on a column portion of the input address ADD. Sense amplifier 513 then receives the differential voltage signal, senses the differential voltage, latches and amplifies it, and outputs the data from the selected SRAM cell on the output data signal DATA.
As described above the memory access cycle includes several steps performed internal to the conventional SRAM memory 500 during each clock cycle. FIG. 6 is a timing diagram of a memory cycle of an SRAM device such as SRAM memory 500. As shown in FIG. 6, the memory access cycle begins with the “Fire WL” operation by firing a word line determined by the row decoder circuit. When the word line fires, the complementary bit lines receive the differential voltage of the SRAM cells along the selected row. During the “Sense Data” operation, the sense amplifiers receive the data that is represented by the differential voltage on the bit line pairs selected by the Y-sel multiplexer. In the example shown in FIG. 6, a precharge operation “Precharge” is performed after the sense amplifier latches the valid data. The precharge in this example is performed at the end of the memory access cycle. The maximum clock frequency for the input clocking signal CLK that can be used for a particular SRAM memory is determined by the amount of time needed to perform the sequential steps of: decoding the address in the row and column decoders, firing the word line for the selected row, sharing the stored data onto the bit line pairs as a differential voltage, sensing the differential voltage in a sense amplifier, and precharging the bit lines for the next memory access. In order to increase performance of a circuit including an SRAM memory such as the example SRAM 500 shown in FIG. 5, the memory cycle time “Tcyc” should be decreased so that the clock frequency can be increased.
Improvements in the operations of SRAM memory devices, and in particular SRAM memory devices arranged for integration into SOCs or into other highly integrated devices, are therefore needed in order to address the deficiencies and the disadvantages of the prior known approaches. Solutions are needed that reduce the memory access cycle time and that reduce the power consumed for the SRAM operations, and which improve the SRAM performance, for example in terms of performance metrics such as the Clk-to-Q access time and SRAM power consumption.